In a pixel array, a pixel comprises, in a semiconductor substrate, a main region corresponding to a photodiode and various regions corresponding to transistor drains/sources. The case where each pixel is associated with an interconnection network comprising two metal levels is considered herein.
FIG. 1 shows an example of a pixel read circuit. Circuit 100 comprises a photodiode 103 coupled to a read node INT via a transfer transistor 105, for example, a MOS transistor, capable of receiving on its gate a transfer voltage TG. A power supply voltage VRT is coupled to node INT via a transistor 107 capable of receiving a reset voltage RST on its gate. A transistor 109 has its drain coupled to power supply voltage VRT, its gate coupled to node INT, and its source coupled to an output node VX via a read transistor 111 capable of receiving a read voltage RD on its gate. The reference voltage of circuit 100 is ground VSS.
In certain pixel arrays, it is provided to insert self-focusing pixels. A self-focusing pixel is a pixel intended to receive only light arriving under a given incidence.
Based on pixels receiving light under different incidences, a focus determination can be performed. Self-focusing pixels comprise shields covering substantially complementary portions of the photodiodes of these pixels, for example, a right-hand portion and a left-hand portion. A self-focusing pixel shielded on the left-hand side (called left-hand pixel hereafter) and a self-focusing pixel shielded on the right-hand side (hereafter, the right-hand pixel) are here distinguished.
The manufacturing of similar pixel arrays comprising “normal” pixels and self-focusing pixels is here considered, the self-focusing pixels being located in determined and identical cells in each array. However, in practice, according to the specific processing unit adopted by a user, the user desires for the left-hand and right-hand pixels to be distributed differently inside of the determined cells which are assigned thereto.